A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A blind channel equalizer device for a radiofrequency receiver suitable for modulating the constant envelope signal of the transmission includes: an adjustable linear digital filter, defined at a point in time by the coefficients) thereof, able to filter an input signal in order to produce an output signal; an estimator able to estimate a power of the input signal; an adapter able to adapt the filter by calculating the coefficients of the filter at a point in time by subtracting, from the filter coefficients at a preceding point in time, the gradient of a cost function assigned with a correction coefficient. The cost function includes a first distance criterion between the square of the output signal and the power, wherein the correction coefficient is a product including a constant convergence coefficient and a scaling coefficient inversely proportional to the square of the power. Also disclosed is a related Radiofrequency receiver.

In a nonlinear signal filtering system, a signal having a series of signal samples is filtered. The signal samples are affected by interactions with adjacent signal samples and nonlinear distortions. The system contains a series of alternating linear system elements and nonlinear system elements that are used for mitigation of distortion resulting from the nonlinear distortions with memory effects. The linear system elements can scale each signal sample in the series of signal samples by scaling parameters and sums a plurality of consecutive scaled signal samples, and the nonlinear system elements can transform the output of the linear system elements according to instantaneous nonlinear functions.

A method of simplifying the encoding of a predetermined number of bits of data into frames including adding error coding bits so that a ratio of the frame length times the baud rate of the frame times he bit packing ratio of the data divided the total bits of data is always an integer. The method may also convolutionally encode the bits of data so that the same equation is also always an integer.

A method for receiving a signal and for rejecting interference in a multichannel receiver, comprises the steps of: reception, transposition and discretization of the signal received on each of the channels of the receiver, so as to obtain a discretized multichannel signal, synchronization of the discretized multichannel signal, computation, on the basis of the discretized and synchronized multichannel signal, of a matrix {circumflex over (R)} of correlation of the total noise, computation, on the basis of the matrix {circumflex over (R)} of correlation of the total noise, of a vector w comprising amplitude phase weighting coefficients of a multichannel filter, and application, to the discretized and synchronized multichannel signal, of a multichannel filtering processing on the basis of the vector w, and then of a single-channel equalization processing to the filtered signal.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A method of simplifying the encoding of a predetermined number of bits of data into frames including adding error coding bits so that a ratio of the frame length times the baud rate of the frame times he bit packing ratio of the data divided the total bits of data is always an integer. The method may also convolutionally encode the bits of data so that the same equation is also always an integer.

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.