One embodiment provides a semiconductor device. The device comprises a substrate having a first face and a second face, a well region, a source region disposed in the well region, a contact region contacting the well region and the source region, a Schottky region, and a source metal layer. A first part of the source metal layer contacts the Schottky region to form a Schottky diode. The Schottky region is surrounded by the contact region and the well region in a first plane perpendicular to a direction from the first face toward the second face.

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.

A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.

An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.