A film forming method includes: repeatedly performing a source gas adsorption process including supplying a source gas containing a metal element to form a nitride film on a substrate in a chamber and purging a residual gas, and a nitriding process including supplying a nitriding gas onto the substrate and purging a residual gas; and supplying a hydrazine-based compound gas as a part or all of the nitriding gas.

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N.sub.2 gas and a NH.sub.3 gas.

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.

The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.

A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

Embodiments described herein generally relate to conformal oxidation processes for flash memory devices. In conventional oxidation processes for gate structures, growth rates have become too fast, ultimately creating non-conformal films. To create a preferred growth rate for SiO.sub.2 on SiN.sub.x films, embodiments in this disclosure use a thermal combustion of a ternary mixture of H.sub.2+O.sub.2+N.sub.2O to gain SiO.sub.2 out of Si containing compounds. Using this mixture provides a lower growth in comparison with using only H.sub.2 and O.sub.2, resulting in a lower sticking coefficient. The lower sticking coefficient allows an optimal amount of atoms to reach the bottom of the gate, improving the conformality in 3D NAND SiO.sub.2 oxidation layers, specifically for ONO replacement tunneling gate formation.

The present disclosure relates to a substrate processing method, and more particularly, to a substrate processing method for improving the physical properties of a thin film formed on a substrate. An embodiment of a substrate processing method according to the present disclosure comprises the steps of: carrying a substrate into a first chamber; a first pressurizing step increasing the pressure in the first chamber so that the pressure in the first chamber reaches a first high-pressure that is higher than the normal pressure; a first depressurizing step decreasing the pressure in the first chamber so that the pressure in the first chamber reaches a second high-pressure that is lower than the first high-pressure and equal to or higher than the normal pressure; a first pressurizing/depressurizing repeating step performing the first pressurizing step and the first depressurizing step repeatedly at a predetermined number of times; and a second depressurizing step decreasing the pressure in the first chamber so that the pressure in the first chamber reaches a first low-pressure that is lower than the normal pressure.

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions.