A semiconductor device includes: a substrate having a groove formed on a main surface; a drift region of a first conductivity type, the drift region having a portion disposed at a bottom part; a well region of a second conductivity type, the well region being disposed in one sidewall to be connected to the drift region; a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region in the sidewall to be away from the drift region; a second semiconductor region of the first conductivity type, the second semiconductor region being disposed to be opposed to the well region via the drift region; and a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region.

A method for manufacturing a semiconductor structure includes: providing a substrate; forming at least a pair of first side walls on the substrate, an interval being provided distance between two first side walls in each pair; forming a second side wall at either side of each of the first side walls by an In-Situ Steam Generation (ISSG) process, and forming a gate oxide layer on the substrate between the two first side walls in each pair; and forming a gate layer on a surface of the gate oxide layer.

A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.

A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.

Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form an extended-gate field effect transistor (EG-FET) on a substrate. The fabrication operations include forming a channel in an EG region of the substrate. A first EG gate dielectric is deposited over the channel at a first low-temperature. A reinforcement treatment is applied to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric. The first low-temperature is selected to be below the second low-temperature; and the second low-temperature is selected to be below a third low-temperature that causes a diffusion of a first type of semiconductor material across an interface and into a second type of semiconductor to exceed a predetermined minimum diffusion level or rate.

A method of manufacturing an integrated circuit. This method includes forming an epitaxial material comprising single crystal piezo material overlying a surface region of a substrate to a desired thickness and forming a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material. Also, the method includes forming a topside landing pad metal and a first electrode member overlying a portion of the epitaxial material and a second electrode member overlying the topside landing pad metal. Furthermore, the method can include processing the backside of the substrate to form a backside trench region exposing a backside of the epitaxial material and the landing pad metal and forming a backside resonator metal material overlying the backside of the epitaxial material to couple to the second electrode member overlying the topside landing pad metal.

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

A method of fabricating an electrode structure may include forming a first gate electrode, performing a removal process on an electrode capping layer formed on the first gate electrode, forming a second gate electrode on the first gate electrode, and nitridating an upper portion of the second gate electrode.

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.