A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

A junction barrier Schottky diode device and a method for fabricating the same is disclosed. In the junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

An insulating film is formed on a front surface of a semiconductor layer in which a trench has been formed. An electric conductor is embedded into the trench, and the insulating film that has been formed on the semiconductor layer surface and that is adjacent to the trench is removed by etching so as to expose the semiconductor layer surface. The semiconductor layer surface is further etched such that the semiconductor layer surface is lowered relative to an upper end of the insulating film covering the inner surface of the trench. After that, a Schottky barrier junction is formed at the semiconductor layer surface.

A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of transistors are formed on the silicon including surface in at least one PMOS region and at least one NMOS region, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region. Pre-silicide cleaning removes oxide from the exposed p-type surface regions and exposed n-type surface regions. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and exposed n-type surface regions. Unreacted metal of the metal layer is stripped.

A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.

Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

There is provided a semiconductor device including: an anode electrode that is provided on a front surface side of a semiconductor substrate; a drift region of a first conductivity type that is provided in the semiconductor substrate; a first anode region of a first conductivity type that is in Schottky contact with the anode electrode; and a second anode region of a second conductivity type that is different from the first conductivity type, in which the first anode region has a doping concentration lower than or equal to a doping concentration of the second anode region, and is spaced from the drift region by the second anode region.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.