Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Provided is a copper alloy sputtering target, wherein, based on charged particle activation analysis, the copper alloy sputtering target has an oxygen content of 0.6 wtppm or less, or an oxygen content of 2 wtppm or less and a carbon content of 0.6 wtppm or less. Additionally provided is a method for manufacturing a copper alloy sputtering target, wherein a copper raw material is melted in a vacuum or an inert gas atmosphere, a reducing gas is thereafter introduced into the melting atmosphere, an alloy element is subsequently added to a molten metal for alloying, and an obtained ingot is processed into a target shape. The present invention aims to provide a copper alloy sputtering target that generates few particles during sputtering, and a method for manufacturing such a sputtering target.

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.

A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill a portion of the through substrate via and cover the horizontal field area. A thermal anneal step to reflow a portion of the first metal layer on the horizontal field area into the through substrate via. A second metal layer is deposited over the first metal layer to fill a remaining portion of the through substrate via. Another aspect of the invention is a device created by the method.

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated using a 0.13 micron (or larger) process, wherein the SOI CMOS transistors include nickel silicide formed on the source/drain regions. Each of the series-connected SOI CMOS transistors has a gate length of about 0.13 microns or more, thereby enabling these SOI CMOS transistors to handle high power RF signals, and exhibit the high breakdown voltages required to implement an RF switch. The nickel silicide regions advantageously contribute to a relatively a low on-resistance (R.sub.ON) of the SOI CMOS transistors, while consuming a relatively small amount of the underlying silicon regions during their fabrication. The SOI CMOS transistors can be fabricated on a relatively thin silicon layer, thereby contributing to a relatively low off capacitance (C.sub.OFF) of the SOI CMOS transistors. As a result, an R.sub.ON*C.sub.OFF value of the RF switch is advantageously minimized.

Methods and apparatus for performing physical vapor deposition in a reactor chamber to form aluminum material on a substrate including: depositing a first aluminum layer atop a substrate to form a first aluminum region having a first grain size and a second aluminum layer atop the first aluminum layer, wherein the second aluminum layer has a second grain size larger than the first grain size; and depositing aluminum atop the second aluminum layer under conditions sufficient to increase the second grain size.

A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.