A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of transistors are formed on the silicon including surface in at least one PMOS region and at least one NMOS region, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region. Pre-silicide cleaning removes oxide from the exposed p-type surface regions and exposed n-type surface regions. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and exposed n-type surface regions. Unreacted metal of the metal layer is stripped.

A method for making EMI shielding layer on a package is disclosed to include the steps of: a) disposing a UV curable adhesive which can be thermally released on a light-transmissive substrate; b) placing the package on the UV curable adhesive in such a way that the UV curable adhesive adheres to and cover a surface of the package having solder pads; c) irradiating UV light toward the light-transmissive substrate to cure the UV curable adhesive; d) forming an EMI shielding layer on the package; and e) thermally releasing the UV curable adhesive.

A method for metallization includes providing a transparent donor substrate (34) having deposited thereon a donor film (36) including a metal with a thickness less than 2 μm. The donor substrate is positioned in proximity to an acceptor substrate (22) including a semiconductor material with the donor film facing toward the acceptor substrate and with a gap of at least 0.1 mm between the donor film and the acceptor substrate. A train of laser pulses, having a pulse duration less than 2 ns, is directed to impinge on the donor substrate so as to cause droplets (44) of the metal to be ejected from the donor layer and land on the acceptor substrate, thereby forming a circuit trace (25) in ohmic contact with the semiconductor material.

An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.

A method of metal-assisted chemical etching comprises forming an array of discrete metal features on a surface of a semiconductor structure, where each discrete metal feature comprises a porous metal body with a plurality of pores extending therethrough and terminating at the surface of the semiconductor structure. The semiconductor structure is exposed to an etchant, and the discrete metal features sink into the semiconductor structure as metal-covered surface regions are etched. Simultaneously, uncovered surface regions are extruded through the pores to form anchoring structures for the discrete metal features. The anchoring structures inhibit detouring or delamination of the discrete metal features during etching. During continued exposure to the etchant, the anchoring structures are gradually removed, leaving an array of holes in the semiconductor structure.

A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.

A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.

Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.

A sputtering target material contains one kind or two or more kinds selected from the group consisting of Ag, As, Pb, Sb, Bi, Cd, Sn, Ni, and Fe in a range of 5 massppm or more and 50 massppm or less, in terms of a total content; and a balance consisting of Cu and an inevitable impurity. In the sputtering target material, in a case in which an average crystal grain size calculated as an area average without twins is denoted by X1 (μm), and a maximum intensity of pole figure is denoted by X2, upon an observation with an electron backscatter diffraction method, Expression (1): 2500>19×X1+290×X2 is satisfied, a kernel average misorientation (KAM) of a crystal orientation measured by an electron backscatter diffraction method is 2.0° or less, and a relative density is 95% or more.