Patent classifications
H01L21/2855
Method of depositing copper using physical vapor deposition
The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
METHODS AND APPARATUS FOR EXTENDED CHAMBER FOR THROUGH SILICON VIA DEPOSITION
An apparatus leverages a physical vapor deposition (PVD) process chamber with a wafer-to-target distance of approximately 400 millimeters to deposit tantalum film on through silicon via (TSV) structures. The PVD process chamber includes a source that is configured with dual magnet source compensation. The PVD chamber also includes an upper electromagnet assembly exterior to the chamber body in close proximity to the source, a magnetron assembly in the source including dual magnets with dual radius trajectories, a shield within the chamber body, and a plurality of grounding loops that are symmetrically spaced about a periphery of a substrate support assembly and are configured to provide an RF ground return path between the substrate support assembly and the shield.
Method for preparing film patterns
A method for preparing film patterns; firstly, a complementary film pattern (1) to a desired film pattern (201) is prepared on a substrate (3) with an erasable agent; secondly, a whole layer of film (2) is formed on the complementary film pattern (1); and thirdly, the desired film pattern (201) is obtained by removing the complementary film pattern (1). The preparation method can simplify the production process and reduce the production cost of the film patterns.
Manufacture method of TFT array substrate and TFT array substrate sturcture
The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).
Contact Structures in Semiconductor Devices
The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.
SPUTTERING SYSTEMS AND METHODS FOR PACKAGING APPLICATIONS
Sputtering systems and methods for packaging applications. In some embodiments, a method for processing a plurality of packaged devices can include forming or providing a first assembly having a stencil and a two-sided adhesive member attached to a first side of the stencil, with the stencil having a plurality of openings, and the two-sided adhesive member having a plurality of openings corresponding to the openings of the stencil. The method can further include attaching the first assembly to a ring to provide a second assembly, with the ring being dimensioned to facilitate a deposition process. The method can further include loading a plurality of packaged devices onto the second assembly such that each packaged device is held by the two-sided adhesive member of the first assembly and a portion of each packaged device extends into the corresponding opening of the two-sided adhesive member.
Bit line utilized in DRAM
A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
SINGLE PROCESS FOR LINER AND METAL FILL
After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
Methods of making integrated circuits including conductive structures through substrates
A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.
Off-angled heating of the underside of a substrate using a lamp assembly
Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed.