Manufacture method of TFT array substrate and TFT array substrate sturcture

Abstract

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Claims

1. A manufacture method of a thin film transistor (TFT) array substrate, comprising steps of: step 1, providing a substrate, and deposing and patterning a first metal layer on the substrate to form a first metal electrode; step 2, forming a gate isolation layer and an island shaped semiconductor layer on the first metal electrode and the substrate; step 3, deposing and patterning a second metal layer on the gate isolation layer and the island shaped semiconductor layer to form a second metal electrode; step 4, deposing and patterning a first layer on the second metal electrode for forming a first protecting layer; step 5, coating a color resist layer on the first protecting layer, and deposing and patterning a second layer on the color resist layer for forming a second protecting layer, and forming a via in the second protecting layer, the color resist layer and the first protecting layer so as to expose a portion of the second metal electrode; and step 6, forming a pixel electrode layer and an organic material layer on the second protecting layer and the second metal electrode, wherein step 6 comprises the following sub-steps: forming a first pixel electrode layer on the second protecting layer and the portion of the second metal electrode exposed in the via; coating the organic material layer on the first pixel electrode layer so that the organic material fills up the via; removing portions of the organic material layer that are located outside and around the via such that a remaining portion of the organic material layer is left in the via and a portion of the first pixel electrode layer that is located outside and around the via is exposed; forming a second pixel electrode layer on the exposed portion of the first pixel electrode layer that is located outside the via and the remaining portion of the organic material layer that is left in the via; and patterning the first pixel electrode layer and the second pixel electrode layer at the same time with one photolithography process to form, respectively, a first pixel electrode and a second pixel electrode that collectively form a pixel electrode that is connected to the second metal electrode through the via.

2. The manufacture method of the TFT array substrate according to claim 1, wherein from the first step to the fourth step, a Physical Vapor Deposition or a Chemical Vapor Deposition is employed for deposing the first metal electrode layer, the gate isolation layer, a semiconductor layer from which the island shaped semiconductor layer was formed, the second metal electrode layer and the first and second protecting layers.

3. The manufacture method of the TFT array substrate according to claim 1, wherein in the first step, the substrate is a glass substrate; in the second step, the island shaped semiconductor layer is formed with amorphous silicon, and the gate isolation layer and the island shaped semiconductor layer are sequentially formed by processes of film formation, exposure, development and etching.

4. The manufacture method of the TFT array substrate according to claim 1, wherein in the fifth step, the color resist layer is a red/green/blue color resist layer, and a diameter of a top of the via is 20 μm, and the organic material layer is formed with a photoresist type material.

5. The manufacture method of the TFT array substrate according to claim 1, wherein the first pixel electrode layer is formed of a material of indium tin oxide (ITO) or indium zinc oxide (IZO) through physical vapor deposition.

6. The manufacture method of the TFT array substrate according to claim 1, wherein the second pixel electrode layer is formed of a material of indium tin oxide (ITO) or indium zinc oxide (IZO) through physical vapor deposition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The technical solution, as well as beneficial advantages, of the present invention will be apparent from the following detailed description of an embodiment of the present invention, with reference to the attached drawings.

(2) In drawings,

(3) FIG. 1 is a flowchart of a manufacture method of a TFT array substrate according to the present invention;

(4) FIG. 2 is a diagram of step 7 in the first embodiment of the manufacture method of the TFT array substrate according to the present invention;

(5) FIG. 3 is a diagram of step 8 in the first embodiment of the manufacture method of the TFT array substrate according to the present invention;

(6) FIG. 4 is a diagram of step 7 in the second embodiment of the manufacture method of the TFT array substrate according to the present invention;

(7) FIG. 5 is a diagram of step 8 in the second embodiment of the manufacture method of the TFT array substrate according to the present invention;

(8) FIG. 6 is a diagram of step 9 in the second embodiment of the manufacture method of the TFT array substrate according to the present invention;

(9) FIG. 7 is a diagram of step 10 in the second embodiment of the manufacture method of the TFT array substrate according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(10) Embodiments of the present invention are described in detail with the technical matters, structural features, achieved objects, and effects with reference to the accompanying drawings as follows.

(11) Please refer to FIG. 1, which is a flowchart of a manufacture method of a TFT array substrate according to the present invention; in this specification, two embodiments are employed for describing the manufacture method of the TFT array substrate.

(12) Please refer from FIG. 1 to FIG. 3. The first embodiment of the manufacture method of the TFT array substrate according to the present invention comprises steps of:

(13) step 1, providing a substrate 1, and deposing and patterning a first metal layer on the substrate 1 to form a first metal electrode 2.

(14) Preferably, the substrate 1 is a glass substrate.

(15) step 2, sequentially forming a gate isolation layer 3 and an island shaped semiconductor layer 4 on the first metal electrode 2 and the substrate 1 by processes of film formation, exposure, development and etching.

(16) Preferably, the island shaped semiconductor layer 4 is formed with amorphous silicon. The gate isolation layer 3 completely covers the first metal electrode 2.

(17) step 3, deposing and patterning a second metal layer on the gate isolation layer 3 and the island shaped semiconductor layer 4 to form a second metal electrode 6.

(18) step 4, deposing and patterning a protecting layer on the second metal electrode 6 for forming the protecting layer 8.

(19) Significantly, from the steps 1 to 4, a Physical Vapor Deposition or a Chemical Vapor Deposition is employed for deposing the first metal electrode 2, the gate isolation layer 3, the island shaped semiconductor layer 4, the second metal electrode 6 and the protecting layers 8.

(20) step 5, coating a color resist layer 7 on the protecting layer 8, and deposing and patterning a protecting layer on the color resist layer 7 for forming the protecting layer 12, and forming a via 81 on the protecting layer 8, the color resist layer 7 and the protecting layer 12.

(21) Specifically, the color resist layer 7 is a RGB color resist layer. Preferably, a diameter of a top of the via 81 is 20 μm.

(22) step 6, deposing and patterning a first pixel electrode layer on the protecting layer 12 and the second metal electrode 6 for forming the first pixel electrode layer 9, and the first pixel electrode layer 9 connects to the second metal electrode 6 with the via 81.

(23) Specifically, a Physical Vapor Deposition is employed for deposing the first pixel electrode layer 9, and material of the first pixel electrode layer 9 is Indium Titanium Oxide (ITO) or Indium Zinc Oxide (IZO).

(24) step 7, coating the organic material layer 10 on the first pixel electrode layer 9, and the organic material layer 10 fills the via 81.

(25) At this moment, not only inside the via 81, the most top layer of the entire array substrate is coated with a flat organic material layer 10. Preferably, the organic material layer 10 is formed with photoresist type material.

(26) step 8, implementing developing process to remove the organic material layer around the via.

(27) Specifically, by controlling the speed of the developing process, the organic material layer 10 remains only inside the via 81 and no residual of the organic material layer 10 exist at the other positions except peripheral of the via 81 when the developing process is accomplished.

(28) In this embodiment, by coating the organic material layer 10, the organic material fills up the inside of the via 81 to reduce the height difference of the landform and to prevent the orientation disorder of the liquid crystal. More significantly, the possibility that the liquid crystal hides bubble in the via 81 is eliminated to diminish the risk of bubble appearance.

(29) Please refer to FIG. 1 and FIGS. 4-7, the second embodiment of the manufacture method of the TFT array substrate according to the present invention comprises steps of:

(30) step 1, providing a substrate 1, and deposing and patterning a first metal layer on the substrate 1 to form a first metal electrode 2.

(31) Preferably, the substrate 1 is a glass substrate.

(32) step 2, sequentially forming a gate isolation layer 3 and an island shaped semiconductor layer 4 on the first metal electrode 2 and the substrate 1 by processes of film formation, exposure, development and etching.

(33) Preferably, the island shaped semiconductor layer 4 is formed with amorphous silicon. The gate isolation layer 3 completely covers the first metal electrode 2.

(34) step 3, deposing and patterning a second metal layer on the gate isolation layer 3 and the island shaped semiconductor layer 4 to form a second metal electrode 6.

(35) step 4, deposing and patterning a protecting layer on the second metal electrode 6 for forming the protecting layer 8.

(36) Significantly, from the step 1 to the step 4, a Physical Vapor Deposition or a Chemical Vapor Deposition is employed for deposing the first metal electrode 2, the gate isolation layer 3, the island shaped semiconductor layer 4, the second metal electrode 6 and the protecting layers 8.

(37) step 5, coating a color resist layer 7 on the protecting layer 8, and deposing and patterning a protecting layer on the color resist layer 7 for forming the protecting layer 12, and forming a via 81 on the protecting layer 8, the color resist layer 7 and the protecting layer 12.

(38) Specifically, the color resist layer 7 is a RGB color resist layer. Preferably, a diameter of a top of the via 81 is 20 μm.

(39) step 6, deposing and patterning a first pixel electrode layer on the protecting layer 12 and the second metal electrode 6.

(40) Specifically, a Physical Vapor Deposition is employed for deposing the first pixel electrode layer 9, and material of the first pixel electrode layer 9 is ITO or IZO.

(41) step 7, coating the organic material layer 10 on the first pixel electrode layer, and the organic material layer 10 fills the via 81.

(42) At this moment, not only inside the via 81, the most top layer of the entire array substrate is coated with a flat organic material layer 10. Preferably, the organic material layer 10 is formed with photoresist type material.

(43) step 8, implementing developing process to remove the organic material layer around the via.

(44) Specifically, by controlling the speed of the developing process, the organic material layer 10 remains only inside the via 81 and no residual of the organic material layer 10 exist at the other positions except peripheral of the via 81 when the developing process is accomplished.

(45) step 9, deposing a second pixel electrode layer on the pixel electrode layer and the organic material layer 10.

(46) Specifically, a Physical Vapor Deposition is employed for deposing the second pixel electrode layer, and material of the second pixel electrode layer is ITO or IZO.

(47) step 10, patterning the first pixel electrode layer and the second pixel electrode layer at the same time with one photolithography process for forming the first pixel electrode layer 9 and the second pixel electrode layer 11, and the first pixel electrode layer 9 and the second pixel electrode layer 11 connects to the second metal electrode 6 with the via 81.

(48) The differences of the second embodiment from the first embodiment is, after the first pixel electrode layer is deposed on the protecting layer 12 in the step 6, the patterning is not implemented temporarily but the steps 7-8 are directly operated. Then, the operation of the step 9 is executed to the substrate obtained in the step 8, i.e. deposing the second pixel electrode layer. Ultimately, the operation of the step 10 is executed for patterning the first pixel electrode layer and the second pixel electrode layer at the same time.

(49) In the second embodiment, after the first pixel electrode layer is deposed, the large via 81 formed by COA process is filled up by coating the organic material layer 10. Then, a planarizing process is implemented thereto. After that, the process of deposing the second pixel electrode layer is implemented again. Ultimately, the patterning the first pixel electrode layer and the second pixel electrode layer is implemented at the same time. Not only the height difference of the landform is effectively eliminated but also the risk of bubble appearance is diminished. Because the pixel electrode layer almost has no height difference of the landform in the entire pixel area, the uniformity of the electric field in the curing process for the VA (Vertical Alignment) liquid crystal mode is increased and the orientation disorder the orientation disorder of the liquid crystal of the liquid crystal can be avoided. Meanwhile, the liquid crystal at the via 81 be effectively controlled and the pixel aperture ratio can be promoted in some degree.

(50) Please refer to FIG. 3. The present invention provides a TFT array substrate structure, comprising a substrate 1, a first metal electrode 2 on the substrate 1, a gate isolation layer 3 positioned on the substrate 1 and completely covering the first metal electrode 2, an island shaped semiconductor layer 4 on the gate isolation layer 3, a second metal electrode 6 on the gate isolation layer 3 and the island shaped semiconductor layer 4, a protecting layer 8 on the second metal electrode 6, a color resist layer 7 on the protecting layer 8, a protecting layer 12 on the color resist layer 7 and a first pixel electrode layer 9 on the protecting layer 12; a via 81 is formed on the protecting layer 8, the color resist layer 7 and the protecting layer 12, and an organic material layer 12 fills the inside of the via 81; the substrate 1 is a glass substrate, and the island shaped semiconductor layer 4 is formed with amorphous silicon, and the color resist layer 7 is a RGB color resist layer, and material of the first pixel electrode layer 9 is ITO or IZO, and the organic material layer 10 is formed with photoresist type material.

(51) Please refer to FIG. 7. The present invention further provides a TFT array substrate structure. The differences from the previous embodiment is that the structure further comprises a second pixel electrode layer 11 on the first pixel electrode layer 9 and the organic material layer 10. Preferably, material of the second pixel electrode layer 11 is ITO or IZO.

(52) In conclusion, according to the manufacture method of the TFT array substrate and the TFT array substrate structure provided by the present invention, by filling the via with organic material and forming two pixel electrode layers to reduce the height difference of the landform thereof. Basically, the pixel utilizing the structure is totally flat and smooth. The effective control area of the pixel electrode is increased to raise the pixel aperture ratio; the risk of bubble appearance is diminished because the larger via is filled up to reduce the height difference of the landform; the uniformity of the curing electric field is increased to prevent the orientation disorder of the liquid crystal because the liquid crystal at the via can be effectively controlled and no landform difference in the electric field.

(53) Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.