A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.

A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

A film containing a prescribed element and carbon is formed on a substrate, by performing a cycle a prescribed number of times, the cycle including: supplying an organic-based source containing a prescribed element and a pseudo catalyst including at least one selected from the group including a halogen compound and a boron compound, into a process chamber in which the substrate is housed, and confining the organic-based source and the pseudo catalyst in the process chamber; maintaining a state in which the organic-based source and the pseudo catalyst are confined in the process chamber; and exhausting an inside of the process chamber.

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.

Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.

Method of forming film stacks and film stacks for electronic devices are described herein. The methods comprise depositing a molybdenum nucleation layer on a gate oxide layer; depositing a molybdenum layer on the molybdenum nucleation layer; and performing a plasma nitridation process to insert nitrogen atoms into the molybdenum layer to form a work function modulating layer having an effective work function ≤ 4.5 eV. The plasma nitridation process comprises exposing the molybdenum layer to a radical-rich plasma comprising one or more of N.sub.2 or NH.sub.3. Some methods further comprise one or more of annealing the work function modulating layer, depositing a conductive layer on the work function modulating layer, or performing an etch process.

Disclosed is a method for removing, from a target substrate having an insulating film with a predetermined pattern formed thereon, a silicon-containing oxide film formed in a silicon portion at a bottom of the pattern. The method includes: forming a carbon-based protective film on the entire surface of the insulating film including the pattern by ALD using a carbon source gas; selectively removing the carbon-based protective film on an upper surface of the insulating film and on the bottom of the pattern by an anisotropic plasma processing; removing the silicon-containing oxide film formed on the bottom of the pattern by etching; and removing a remaining portion of the carbon-based protective film.