H01L21/28556

Bi-Layer Alloy Liner For Interconnect Metallization And Methods Of Forming The Same

A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

NON-SHADOW FRAME PLASMA PROCESSING CHAMBER

Embodiments described herein generally relate to a substrate support assembly. The substrate support assembly includes a support plate and a ceramic layer. The support plate has a top surface. The top surface includes a substrate receiving area configured to support a large area substrate and an outer area located outward of the substrate receiving area.

Selective growth for high-aspect ratio metal fill

An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

FABRICATION OF MULTI THRESHOLD-VOLTAGE DEVICES
20170301551 · 2017-10-19 ·

A method of fabricating multi V.sub.th devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second regions; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

Cobalt-containing compounds, their synthesis, and use in cobalt-containing film deposition

Cobalt-containing compounds, their synthesis, and their use for the deposition of cobalt containing films are disclosed. The disclosed cobalt-containing compounds have one of the following formulae: wherein each of R.sup.1, R.sup.2, R.sup.3, R.sup.4 and R.sup.5 is independently selected from Hydrogen; halogen; linear, cyclic or branched hydrocarbons; primary amino ligands (—NHR); or secondary amino ligands (—NRR′), with R and R′ independently being H or a linear, cyclic or branched hydrocarbon, provided at least one of R.sup.1, R.sup.2, or R.sup.3 in Formula I and R.sup.4 or R.sup.5 in Formula II is an amino ligand. ##STR00001##

Contact structures
11257718 · 2022-02-22 · ·

The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Semiconductor device structure with barrier layer

A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer. The first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, the contact layer passes through the first barrier layer and extends into the dielectric structure, and the first barrier layer passes through the second barrier layer and extends into the dielectric structure.

Cobalt precursor and methods for manufacture using the same

The inventive concept relates to a cobalt precursor, a method for manufacturing a cobalt-containing layer using the same, and a method for manufacturing a semiconductor device using the same. More particularly, the cobalt precursor of the inventive concept includes at least one compound selected from the group consisting of a compound of Formula 1 and a compound of Formula 2.

Semiconductor arrangement and method of making

A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

NANOCRYSTALLINE GRAPHENE AND METHOD OF FORMING NANOCRYSTALLINE GRAPHENE

Provided are nanocrystalline graphene and a method of forming the nanocrystalline graphene through a plasma enhanced chemical vapor deposition process. The nanocrystalline graphene may have a ratio of carbon having an sp.sup.2 bonding structure to total carbon within the range of about 50% to 99%. In addition, the nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm.