FABRICATION OF MULTI THRESHOLD-VOLTAGE DEVICES

Abstract

A method of fabricating multi V.sub.th devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second regions; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

Claims

1. A method comprising: forming a high-k dielectric layer over a substrate; forming a first titanium nitride (TiN) layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second regions; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

2. The method according to claim 1, further comprising: depositing tungsten (W) over the first, second, and third TiN layers subsequent to removing the exposed first barrier layer, for a p-type device.

3. The method according to claim 1, further comprising: forming an n-type work-function (WF) metal layer over first, second, and third TiN layers subsequent to removing the exposed first barrier layer; and depositing W over the n-type WF metal layer, for an n-type device.

4. The method according to claim 1, comprising: depositing the TiN and barrier layers by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) with no air break between layers.

5. The method according to claim 1, wherein the first barrier layer and the second barrier layer comprise titanium silicide nitride (TiSiN).

6. The method according to claim 1, wherein the first barrier layer and the second barrier layer comprise tantalum nitride (TaN) or lanthanum nitride (LaN).

7. The method according to claim 1, comprising removing the third TiN layer in the second and third regions and the second TiN layer in the third region by etching.

8. The method according to claim 7, comprising: removing the first and second barrier layers by etching selective to TiN.

9. The method according to claim 8, comprising etching the first barrier layer by a wet etch or reactive ion etching (RIE).

10. The method according to claim 8, comprising etching the second barrier layer by a wet etch.

11. The method according to claim 1, comprising removing the first and second masking layers by ashing.

12. The method according to claim 1, comprising forming the barrier layer to a thickness of 5 angstroms (Å) to 20 Å.

13. A device comprising: a high-k dielectric layer over a substrate; a first titanium nitride (TiN) layer over the high-k dielectric layer in first, second, and third regions; a first barrier layer over the first TiN layer in the second and third regions; a second TiN layer over the first barrier layer; a second barrier layer over the second TiN layer in the third region; and a third TiN layer over the second barrier layer.

14. The device according to claim 13, further comprising: tungsten (W) over the first, second, and third TiN layers, for a p-type device.

15. The device according to claim 13, further comprising: an n-type work-function (WF) metal layer over first, second, and third TiN layers; and tungsten (W) over the n-type WF metal layer, for an n-type device.

16. The device according to claim 15, wherein: the n-type work-function (WF) metal layer comprises titanium carbide (TiC).

17. The device according to claim 13, wherein the first barrier layer and the second barrier layer comprise titanium silicide nitride (TiSiN).

18. The device according to claim 13, wherein the first barrier layer and the second barrier layer comprise tantalum nitride (TaN).

19. The device according to claim 1, wherein the barrier layer has a thickness of 5 angstroms (Å) to 20 Å.

20. A method comprising: forming a high-k dielectric layer over a substrate; forming a first titanium nitride (TiN) layer over the high-k dielectric layer to a thickness of 5 Å to 20 Å; forming over the first TiN layer a first barrier layer comprising titanium silicide nitride (TiSiN) or tantalum nitride (TaN) to a thickness of 5 Å to 20 Å; forming a second TiN layer over the first barrier layer to a thickness of 5 Å to 20 Å; forming over the second TiN layer a second barrier layer comprising titanium silicide nitride (TiSiN) or tantalum nitride (TaN) to a thickness of 5 Å to 20 Å; forming a third TiN layer over the second barrier layer to a thickness of 5 Å to 20 Å; forming a first masking layer over the third TiN layer in a first region; etching the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer by ashing; etching the exposed second barrier layer selective to TiN; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second regions; etching the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer by ashing; etching the exposed first barrier layer selective to TiN; depositing tungsten (W) over the first, second, and third TiN layers subsequent to removing the exposed first barrier layer, for a p-type device; and forming an n-type work-function (WF) metal layer over first, second, and third TiN layers subsequent to removing the exposed first barrier layer and depositing W over the n-type WF metal layer, for an n-type device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0014] FIGS. 1A through 1K schematically illustrate sequential steps of a method of forming multi V.sub.th devices, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

[0015] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

[0016] The present disclosure addresses and solves the current problem of a damaged TiN to high-k dielectric interface attendant upon chemical attack from repeated removal and replacement of the TiN layer to form a multi V.sub.th device. In accordance with embodiments of the present disclosure, a multi-stack of alternating barrier layers and TiN layers is formed over the high-k dielectric layer by using a clustered tool. Then, different portions of the multi-stack are etched down to different barrier layers to obtain desired thicknesses to meet the device V.sub.th requirements.

[0017] Methodology in accordance with embodiments of the present disclosure includes forming a high-k dielectric layer (e.g., lanthanum oxide (LaO.sub.2)) over a substrate. Next, a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer are formed consecutively over the high-k dielectric layer. Then, a first masking layer is formed over the third TiN layer in a first region, and the third TiN layer is removed in second and third regions, exposing the second barrier layer in the second and third regions. Next, the first masking layer is removed. Then, the exposed second barrier layer is removed. Subsequently, a second masking layer is formed over the third TiN layer in the first region and the second TiN layer in the second regions. Then, the second TiN layer in the third region is removed, exposing the first barrier layer in the third region. Next, the second masking layer is removed. Finally, the exposed first barrier layer is removed.

[0018] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0019] FIGS. 1A through 1K schematically illustrate sequential steps of a method of forming multi V.sub.th devices including barrier layers between TiN layers for reduced etching of TiN layers, in accordance with an exemplary embodiment. Adverting to FIG. 1A, a high-k dielectric layer 101 is formed over a substrate, such as a silicon wafer (not shown for illustrative convenience). The high-k dielectric may include materials with dipole formation materials such as LaO.sub.2 Next, a first TiN layer 103, a first barrier layer 105, a second TiN layer 107, a second barrier layer 109, and a third TiN layer 111 are consecutively deposited over the high-k dielectric layer 101 in three regions for each device to be formed (a first region where a thick TiN layer is required, a second region where a thinner TiN layer is needed, and a third region where a thin TiN is required). These layers may be deposited with an air break or without an air break with CVD, ALD or PVD. The high-k dielectric layer 101 is formed to a thickness of 5 Å to 20 Å. The first TiN layer 103, the second TiN layer 107 and the third TiN layer 111 are each formed to a thickness of 5 Å to 20 Å. The first barrier layer 105 and the second barrier layer 109 are each formed of TiSiN or TaN or LaN, and are each deposited to a thickness of 5 Å to 20 Å. The TiN and barrier layers may all be deposited in a clustered tool.

[0020] Adverting to FIG. 1B, a masking layer 113 is formed over an upper surface of the third TiN layer 111 in a first region. The masking layer 113 may be formed of silicon oxide or photoresist. Next, as illustrated in FIG. 1C, the third TiN layer 111 is removed in the second and third regions by etching, thereby exposing the second barrier layer 109 in the second and third regions. The TiN layer may be etched by RIE or by a wet etch process. Then, the first masking layer 113 is removed by ashing, for example with diazene (N.sub.2H.sub.2) plasma, as depicted in FIG. 1D. Subsequently, as illustrated in FIG. 1E, the exposed second barrier layer 109 is removed by RIE or a wet etch selective to TiN, thereby exposing the second TiN layer 107 in the second and third regions. A wet etching may use an etching solution of SC1, or a dry etching may use Cl.sub.2/He, HCl/He, Cl.sub.2/He+O.sub.2, CF4/N2, or Cl2/H2/Ar.

[0021] Adverting to FIG. 1F, a second masking layer 115 is formed over the third TiN layer 111 in the first region and the second TiN layer 109 in the second region. The masking layer 115, like masking layer 113, is formed of silicon oxide or photoresist. Next, as illustrated in FIG. 1G, the second TiN layer 107 is removed in the third region by etching, thereby exposing the first barrier layer 105 in the third region. Then, the masking layer 115 is removed by ashing, as depicted in FIG. 1H. Subsequently, as illustrated in FIG. 1I, the exposed first barrier layer 105 is removed by a wet etch or RIE selective to TiN, thereby exposing the first TiN layer 103 in the third region.

[0022] As illustrated in FIG. 1J, subsequent to removing the exposed first barrier layer 105, W 117 is deposited over the first TiN layer 103, second TiN layer 107, and third TiN layer 111 for a p-type device. The resulting device has a thin TiN layer for a high V.sub.th, a thick TiN for a low V.sub.th, and a medium thickness TiN for a middle V.sub.th.

[0023] Alternatively, for an n-type device, subsequent to removing the exposed first barrier layer 105, an n-type WF metal layer 119 is formed over the first TiN layer 103, the second TiN layer 107, and the third TiN layer 111, as illustrated in FIG. 1K. The n-type WF metal layer may be formed, for example, of titanium carbide (TiC). Then, W is deposited over the n-type WF metal layer to complete the n-type device. The resulting device includes a thin TiN layer for a low V.sub.th, a thick TiN for a high V.sub.th, and a medium thickness TiN for a middle V.sub.th.

[0024] The embodiments of the present disclosure can achieve several technical effects, such as, the TiN to high-k dielectric interface. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure enjoys industrial applicability in any of various types of highly integrated IC devices, particularly for the 14 nm and 10 nm technology nodes and beyond.

[0025] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.