In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

An electronic device can include a gate structure. In an embodiment, the gate structure can include a gate electrode including a doped semiconductor material, a metal-containing member, a pair of conductive sidewall spacers. The first metal-containing member can overlie the gate electrode. The conductive sidewall spacers can overlie the gate electrode and along opposite sides of the first metal-containing member. In another embodiment, the gate structure can include a gate electrode, a first metal-containing member overlying the gate electrode, and a second metal-containing member overlying the first metal-containing member. The first metal-containing member can have a length that is greater than the length of the second metal-containing member and substantially the same length as the gate electrode.

A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.

N-polar transistor structures have relied on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers as commercially viable wet etchants do not exist. The present disclosure reports on methods for the fabrication of N-polar III-N transistors using wet etches along with transistor structures that are enabled by the availability of wet-etches.

Semiconductor device includes a semiconductor layer, an insulating film provided on the semiconductor layer and having an opening formed therein, a gate electrode connected to the semiconductor layer through opening, a protection film covering gate electrode, and a Ni oxide film, wherein the insulating film has a first surface on the semiconductor layer side and a second surface opposite to the first surface, and the gate electrode has a third surface facing the second surface and spaced apart from the second surface and a fourth surface connecting the second surface and the third surface. The gate electrode includes a Ni film constituting the third surface and the fourth surface, and the Ni oxide film covers the Ni film on the third surface and the fourth surface. The protection film covers the third surface and the fourth surface by being placed over Ni oxide film.

A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.

A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.

An object of the technique disclosed in the Description is to provide a semiconductor device that reduces a gate leakage current without degrading its high-frequency characteristic. A semiconductor device relating to the technique disclosed in the Description includes a nitride semiconductor layer, a first insulating film partly disposed on the upper surface of the nitride semiconductor layer, and a gate electrode provided to have a lower surface that is at least partly in contact with the upper surface of the nitride semiconductor layer that is exposed without being covered with the first insulating film. The first insulating film is provided to be in contact with a side surface of the gate electrode. The first insulating film contains a transition metal.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer and a gate structure. The gate structure includes a first portion and a second portion on the first portion. The first portion is on the III-V material layer. The first portion has a first surface and a second surface opposite to the first surface and adjacent to the III-V material layer. A length of the second surface of the first portion of the gate structure is less than a length of the first surface of the first portion of the gate structure. A length of the second portion of the gate structure is less than the length of the first portion of the gate structure.