H01L21/31055

Polishing liquid, polishing liquid set and polishing method

According to an aspect of the present invention, there is provided a polishing liquid containing abrasive grains, a hydroxy acid, a polyol, at least one zwitterionic compound selected from the group consisting of an aminocarboxylic acid and an aminosulfonic acid, and a liquid medium, in which a zeta potential of the abrasive grains is positive, an isoelectric point of the aminocarboxylic acid is smaller than 7.0, and pKa of the aminosulfonic acid is larger than 0.

Semiconductor structure and fabricating method thereof

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Fin Field-Effect Transistor With Void and Method of Forming The Same

A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Method of semiconductor integrated circuit fabrication

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

METHOD FOR SELECTIVELY MANUFACTURING MATERIAL LAYER AND TARGET PATTERN

A material layer manufacturing method is provided. The material layer manufacturing method may comprise the steps of: preparing a substrate having a base pattern formed thereon; providing a first precursor on the substrate having the base pattern formed thereon, in a state where a first voltage is applied to the base pattern; and providing a second precursor on the substrate having the first precursor provided thereon, in a state where a second voltage is applied to the base pattern, to form, on the substrate having the base pattern formed thereon, a material layer resulting from the reaction of the first precursor with the second precursor.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES USING DIRECTIONAL PROCESS

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

GAP-FILL LAYERS, METHODS OF FORMING THE SAME, AND SEMICONDUCTOR DEVICES MANUFACTURED BY THE METHODS OF FORMING THE SAME

A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
20220139923 · 2022-05-05 ·

The present application relates to the technical field of manufacturing semiconductor, and in particular to a method of manufacturing semiconductor structure and a semiconductor structure. The method of manufacturing semiconductor structure includes: forming a conductive layer on a substrate, and removing part of the conductive layer to form a contact structure composed of a plurality of contact pads; where each of the contact pads is electrically connected to a transistor structure on the substrate; and, after the contact pads are formed, removing residual core on top ends of the contact pads away from the substrate by dry etching.

Contact formation method and related structure

A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

CMP slurry solution for hardened fluid material

A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H.sub.2O.sub.2), ammonium persulfate ((NH.sub.4).sub.2S.sub.2O.sub.8), peroxymonosulfuric acid (H.sub.2SO.sub.5), ozone (O.sub.3) in de-ionized water, and sulfuric acid (H.sub.2SO.sub.4).