A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, and a semiconductor structure. The method for fabricating a semiconductor structure includes: providing a substrate covered with a conductive layer; removing part of the conductive layer by dry etching to form a first groove, a depth of the first groove being less than a thickness of the conductive layer, and there being polymer residue on a groove wall of the first groove; removing part of the conductive layer corresponding to the groove wall and a groove bottom of the first groove to form conductive lines and a second groove between adjacent two of the conductive lines; and forming a passivation layer filled into the second groove.

The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.

A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

A chemical mechanical polishing method may include polishing a polishing object at a first temperature using a chemical mechanical polishing slurry; and removing the chemical mechanical polishing slurry on the polishing object at a second temperature different from the first temperature. The chemical mechanical polishing slurry may include abrasive particles, a thermoresponsive inhibitor, and deionized water. The thermoresponsive inhibitor may include a thermoresponsive polymer exhibiting a phase-transition between the first temperature and the second temperature. The thermoresponsive polymer may be adsorbed to the hydrophobic layer at the first temperature and desorbed from the hydrophobic layer at the second temperature.