A method for selective etching of silicon oxide relative to silicon nitride includes exposing a substrate to a first gas that forms a first layer on the silicon oxide film and a second layer on the silicon nitride film, where the first gas contains boron, aluminum, or both boron and aluminum, exposing the substrate to a nitrogen-containing gas that reacts with the first layer to form a first nitride layer on the silicon oxide film and reacts with the second layer to form a second nitride layer on the silicon nitride film, where a thickness of the second nitride layer is greater than a thickness of the first nitride layer. The method further includes exposing the substrate to an etching gas that etches the first nitride layer and silicon oxide film, where the second nitride layer protects the silicon nitride film from etching by the etching gas.

A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.

A plasma processing method for a workpiece in a plasma processing apparatus includes (i) performing a first plasma processing on a workpiece, and (ii) performing a second plasma processing on the workpiece. Power of second radio frequency waves set in the second plasma processing is greater than the power of the second radio frequency waves set in the first plasma processing. In the second plasma processing, a magnetic field distribution having a horizontal component on an edge side of the workpiece greater than a horizontal component on a center of the workpiece is formed by an electromagnet.

A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.

A method for etching a surface including obtaining a substrate comprising a material; reacting a surface of a substrate with a reactant, comprising a gas or a plasma, to form a reactive layer on the substrate, the reactive layer comprising a chemical compound including the reactant and the material; and wet etching or dissolving the reactive layer with a liquid wet etchant of solvent that selectively etches or dissolves the reactive layer but not the substrate.

A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm.sup.2 or more.

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

The present disclosure provides a method for forming a thermoelectric device, comprising providing a semiconductor substrate and providing a first layer of an etching material adjacent to the semiconductor substrate. The etching material facilitates the etching of the semiconductor substrate upon exposure to an oxidizing agent and a chemical etchant. Next, a second layer of a semiconductor oxide is provided adjacent to the first layer, and the second layer is patterned to form a pattern of holes or wires. The second layer and first layer are then sequentially etched to expose portions of the semiconductor substrate. Exposed portions of the semiconductor substrate are then contacted with an oxidizing agent and a chemical etchant to transfer the pattern to the semiconductor substrate.