The present disclosure provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die, forming a first mask layer on the second die, forming a first opening along the first mask layer and the second die, and extending to the first die, forming isolation layers on sidewalls of the first opening, forming protection layers covering upper portions of the isolation layers, and forming a conductive filler layer in the first opening.

A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.

Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

A method for preparing a biological material for implanting provides irradiating at least a portion of the surface of the material with an accelerated Neutral Beam.

Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlO.sub.x). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

Compositions useful for the selective removal of silicon nitride materials relative to polysilicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon are provided. The compositions of the invention are particularly useful in the etching of 3D NAND structures.

In an example of the present disclosure, 3D memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.