Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

Apparatus and methods are disclosed for sample preparation, suitable for online or offline use with multilayer samples. Ion beam technology is leveraged to provide rapid, accurate delayering with etch stops at a succession of target layers. In one aspect, a trench is milled around a region of interest (ROI), and a conductive coating is developed on an inner sidewall. Thereby, reliable conducting paths are formed between intermediate layers within the ROI and a base layer, and stray current paths extending outside the ROI are eliminated, providing better quality etch progress monitoring, during subsequent etching, from body or scattered currents. Ion beam assisted gas etching provides rapid delayering with etch stops at target polysilicon layers. Uniform etching at deep layers can be achieved. Variations and results are disclosed.

At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner side wall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner side wall of the trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage may be enhanced, adverse effects of the surface charge may be reduced, and chip size may be further reduced.

In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

A method of manufacturing a chip package is provided. The method includes patterning at least one chip pad of a chip to form a patterned structure in the at least one chip pad, the patterned structure including at least one predefined recess, and encapsulating the chip with encapsulating material, thereby filling the at least one predefined recess.

A replacement metal gate transistor is described. Various examples provide a replacement metal gate transistor including a trench, a first sidewall and a second sidewall. A layer is disposed in the trench where the layer has a bottom section disposed on a bottom of the trench and sidewall sections disposed on the first and second sidewalls, wherein the sidewall sections of the layer are at least 50% thinner than the bottom section of the layer.

A method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

A method and system for improved planar deprocessing of semiconductor devices using a focused ion beam system. The method comprises defining a target area to be removed, the target area including at least a portion of a mixed copper and dielectric layer of a semiconductor device; directing a precursor gas toward the target area; and directing a focused ion beam toward the target area in the presence of the precursor gas, thereby removing at least a portion of a first mixed copper and dielectric layer and producing a uniformly smooth floor in the milled target area. The precursor gas causes the focused ion beam to mill the copper at substantially the same rate as the dielectric. In a preferred embodiment, the precursor gas comprises methyl nitroacetate. In alternative embodiments, the precursor gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.