Patent classifications
H01L21/32139
PICK-UP STRUCTURE FOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A pick-up structure for a memory device and method for manufacturing memory device are provided. The pick-up structure includes a substrate and a plurality of pick-up electrode strips. The substrate has a memory cell region and a peripheral pick-up region adjacent thereto. The pick-up electrode strips are parallel to a first direction and arranged on the substrate in a second direction. The second direction is different from the first direction. Each pick-up electrode strip includes a main part in the peripheral pick-up region and an extension part extending from the main part to the memory cell region. The main part is defined by fork-shaped patterns of a first mask layer. The extension part has a width less than that of the main part, and the extension part has a side wall surface aligned with a side wall surface of the main part.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
CONTROL OF MASK CD
A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.
High electron mobility transistor and fabrication method thereof
The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.
PHOTORESIST COMPOSITIONS FOR EUV AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME
Provided are photoresist compositions for EUV and methods for manufacturing a semiconductor device using the same. The photoresist compositions for EUV include a photosensitive resin, a photoacid generator, and an additive, wherein the additive comprises a copolymer including a first repeating unit that includes a fluoroalkyl group or hydrocarbon group substituted with one or more fluoroalkyl group(s), and a second repeating unit that includes a sulfonic acid group and an amide group.
Temperature controlling apparatus
A temperature controlling apparatus includes a platen, a first and a second conduits, and a first and a second outlet thermal sensors. The first conduit includes a first inlet, a first outlet, and a first heater. A first fluid enters the first inlet and exits the first outlet, the first heater heats the first fluid to a first heating temperature, and the first fluid is dispensed on the platen. The second conduit includes a second inlet, a second outlet, and a second heater. A second fluid enters the second inlet and exits the second outlet, the second heater heats the second fluid to a second heating temperature, and the second fluid is dispensed on the platen. The first and the second outlet thermal sensors are respectively disposed at the first and the second outlets to sense temperatures of the first and the second fluid.
SEMICONDUCTOR STRUCTURE INCLUDING MIM CAPACITOR AND METHOD OF FORMING THE SAME
A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
A semiconductor structure formed by the method for forming the semiconductor structure includes: a substrate, on which an insulating layer is formed; metal conductive layers located on the insulating layer; and an isolation structure located between two adjacent ones of the metal conductive layers.
COMPOSITION FOR SEMICONDUCTOR PHOTORESIST, AND PATTERN FORMATION METHOD USING SAME
Disclosed are a semiconductor photoresist composition and a method of forming patterns using the semiconductor photoresist composition. The semiconductor photoresist composition includes an organometallic compound represented by Chemical Formula 1 and a solvent and a method of forming patterns using the same.