A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.

According to one embodiment, a substrate processing device includes a stage configured to mount a substrate, a mold having a first surface facing an upper surface of an outer peripheral edge of the substrate and a second surface facing a side surface of an outer peripheral continuous with the upper surface of the outer peripheral edge, a mold moving mechanism configured to move the mold to bring the first surface close to the upper surface of the outer peripheral edge of the substrate and the second surface close to the side surface of the outer peripheral of the substrate, and a nozzle arranged in the mold, wherein the nozzle ejects resist.

Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an intermediate semiconductor structure; etching a part of the mandrel layer, exposing a part of the polycrystalline silicon layer, and forming a first spacing group; depositing a first spacing layer, and covering the first spacing group and an exposed area of the polycrystalline silicon layer; removing the first spacing group and a part of the first spacing layer, exposing a part of the polycrystalline silicon layer, and forming a second spacing group; depositing a second spacing layer, and covering the second spacing group and an exposed area of the polycrystalline silicon layer; removing the second spacing group and a part of the second spacing layer, exposing a part of the polycrystalline silicon layer, and forming a third spacing group.

Embodiments provide method for forming a connecting pad. The method includes: providing a substrate; sequentially forming a conductive layer, a first pattern definition layer and a second pattern definition layer on a surface of the substrate; sequentially forming three groups of patterns intersecting with each other at 120° on the second pattern definition layer, an intersection portion of the three groups of patterns forming a hexagonal pattern definition structure on the second pattern definition layer; transferring the pattern definition structure downward, and etching away a portion of the first pattern definition layer, such that the remaining first pattern definition layer forms a columnar structure, wherein a bottom of the columnar structure is circular in shape under an action of an etching load effect; and etching the conductive layer by using the remaining first pattern definition layer as a mask, such that the remaining conductive layer forms a circular connecting pad.

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

A method includes: forming a patterned dielectric layer, including a predetermined word line region and a predetermined pick-up neck region being separated by a first distance, and the patterned dielectric layer within the predetermined pick-up neck region has a second distance, wherein the first distance is smaller than or equal to the second distance; forming a spacer on sidewalls of the patterned dielectric layer; cutting off the spacer of a connecting portion of the predetermined word line region from the spacer of a remaining portion of the predetermined word line region; forming a mask pattern, including a first portion across the connecting portion and the predetermined pick-up neck region, wherein the spacer at the remaining portion is spaced apart from the first portion; and forming a dummy structure, word lines, and pick-up necks, wherein the dummy structure is located between the word lines and the pick-up necks.

A method for fabricating a semiconductor device includes following steps: A patterned mask layer including a plurality of standing walls and a covering part is formed on a surface of a semiconductor substrate, wherein two adjacent standing walls define a first opening exposing a part of the surface, and the covering part blankets the surface. A first patterned photoresist layer is formed to partially cover the covering part. A first etching process is performed to form a first trench in the substrate, passing through the surface and aligning with the first opening. A portion of the patterned mask layer is removed to form a second opening exposing another portion of the surface. A second etching process is performed to form a second trench in the substrate and define an active area on the surface. The depth of the first trench is greater than that of the second trench.

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.