A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.

A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.

An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.

Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

A method for manufacturing multi-voltage devices is provided. The method includes forming a pair of logic gate stacks in a logic region of a semiconductor substrate and a pair of device gate stacks in a multi-voltage device region. The pair of logic gate stacks and the pair of device gate stacks include first dummy gate material. The pair of device gate stacks also includes a work function tuning layer. The method further includes depositing second dummy gate material over the pair of logic gate stacks. The first dummy gate material and the second dummy gate material from over a first logic gate stack of the pair of logic gate stacks are replaced with an n-type material. The first dummy gate material and the second dummy gate material from over a second logic gate stack of the pair of logic gate stacks are replaced with a p-type material.

In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.

A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.