A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of:

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Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH).sub.2, —NH.sub.2, —NHR, —NR.sub.2, —SH, —RSH, or —R(SH).sub.2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R.sub.1, and R.sub.2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.

A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials.

The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.