A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first gate insulation film and a first work function film disposed on the first gate insulation film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second gate insulation film and a second work function film disposed on the second gate insulation film, wherein a first thickness of the first work function film in a second direction intersecting the first direction is different from a second thickness of the second work function film in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

A method for manufacturing a vertical transistor device includes forming a plurality of fins on a substrate, and forming a gate dielectric layer on the fins and on the substrate adjacent the fins. In the method, one or more sacrificial layers are formed on the gate dielectric layer, and portions of the gate dielectric layer and the one or more sacrificial layers are removed to define a plurality of gate regions. The method also includes depositing a dielectric fill layer in gaps left by the removed gate dielectric and sacrificial layers, and selectively removing the remaining portions of the one or more sacrificial layers to form a plurality of vacant areas in the gate regions. First and second gate structures are respectively formed in first and second vacant areas of the plurality of vacant areas. The first and second gate structures are recessed to a uniform height.

A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

Techniques are provided herein to form semiconductor devices having different work function metals over different devices. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to gate-all-around (GAA) transistors. In an example, neighboring semiconductor devices each include a different work function to act as the device gate electrode for each semiconductor device. More specifically, a first semiconductor device may be a p-channel GAA transistor with a first work function metal around the various nanoribbons of the transistor, while the second neighboring semiconductor device may be an n-channel GAA transistor with a second work function metal around the various nanoribbons of the transistor. No portions of the first work function metal are present around the nanoribbons of the second semiconductor device and no portions of the second work function metal are present around the nanoribbons of the first semiconductor device.

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

A semiconductor device structure includes a semiconductor substrate, a first device formed in the first region of the semiconductor substrate and a second device formed in the second region of the semiconductor substrate. The first device includes a first gate structure on the semiconductor substrate. The first gate structure includes a first gate dielectric layer on the semiconductor substrate and a first gate layer on the first gate dielectric layer. The second device includes a second gate structure on the semiconductor substrate. The second gate structure includes a second gate dielectric layer on the semiconductor substrate and a second gate layer on the second gate dielectric layer. The first gate dielectric layer of the first device and the second gate dielectric layer of the second device have different dielectric material compositions.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.