Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

A novel dielectric cap structure for VTFET device fabrication is provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a substrate using fin hardmasks, including a first fin(s) and a second fin(s); depositing a liner over the fins and the fin hardmasks; selectively forming first hardmask caps on top of the fin hardmasks/liner over the first fin(s); forming first bottom source and drain at a base of the first fin(s) while the fin hardmasks/liner over the first fin(s) are preserved by the first hardmask caps; selectively forming second hardmask caps on top of the fin hardmasks/liner over the second fin(s); and forming second bottom source and drains at a base of the second fin(s) while the fin hardmasks/liner over the second fin(s) are preserved by the second hardmask caps. A device structure is also provided.

A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a first electrode comprising a first portion, a second portion, and a sheet portion connecting the first portion to the second portion. A ferroelectric material is over the sheet portion. A second electrode is over the ferroelectric material.

The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.

A semiconductor structure includes a substrate, a circuit region, and a seal ring surrounding the circuit region. The circuit region includes two first source/drains, first semiconductor layers connecting the two first source/drains, and a first gate disposed between the two first source/drains and wrapping around each of the first semiconductor layers. The seal ring includes two epitaxially grown semiconductor structures, second semiconductor layers, third semiconductor layers, and a second gate. The second and the third semiconductor layers are alternately stacked one over another to form a stack of layers. A topmost layer of the stack is one of the third semiconductor layers. The second gate is disposed between the two epitaxially grown semiconductor structures and above the topmost layer of the stack. The first and the third semiconductor layers include a first semiconductor material. The second semiconductor layers include a second semiconductor material different from the first semiconductor material.

Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes first nanostructures directly over a first portion of a substrate and second nanostructures directly over a second portion of the substrate, n-type source/drain features coupled to the first nanostructures and p-type source/drain features coupled to the second nanostructures, and an isolation structure disposed between the first portion of the substrate and the second portion of the substrate. The isolation structure includes a first smiling region in direct contact with the first portion of the substrate and having a first height. The isolation structure also includes a second smiling region in direct contact with the second portion of the substrate and having a second height, the first height is greater than the second height.

A semiconductor device includes a substrate including a first active fin and a second active fin respectively extending in a first direction, the substrate having a recess between the first and second active fins, a device isolation film on the substrate, first and second gate structures on the first and second active fins, respectively, and extending in a second direction, and a field separation layer having a first portion between the first and second active fin and in the recess, and a second portion extending from both sides of the first portion in the second direction to an upper surface of the device isolation film. The recess has a bottom surface lower in a third direction intersecting the first direction and the second direction than the upper surface of the device isolation film, and a region of the upper surface of the device isolation film has a flat surface.