The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

A method of forming semiconductor device is disclosed. A substrate having a logic circuit region and a memory cell region is provided. A first transistor with a first gate is formed in the logic circuit region and a second transistor with a second gate is formed in the memory cell region. A stressor layer is deposited to cover the first transistor in the logic circuit region and the second transistor in the memory cell region. The first transistor and the second transistor are subjected to an annealing process under the influence of the stressor layer to recrystallize the first gate and the second gate.

Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

An IC includes a first and second active areas (AA) with a second conductivity type, a source and drain region, and an LDD extension to the source and drain in the first AA having a first conductivity type. A first bent-gate transistor includes a first gate electrode over the first AA extending over the corresponding LDD. The first gate electrode includes an angled portion that crosses the first AA at an angle of 45° to 80°. A second transistor includes a second gate electrode over the second AA extending over the corresponding LDD including a second gate electrode that can cross an edge of the second AA at an angle of about 90°. A first pocket distribution of the second conductivity type provides a pocket region under the first gate electrode. A threshold voltage of the first bent-gate transistor is ≥30 mV lower as compared to the second transistor.

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Embodiments of the invention are directed to a fabrication method that includes forming a first-region channel over a first region of a substrate, wherein the first-region channel further includes lateral sidewalls having a length (L), a first end sidewall having a first width (W1), and a second end sidewall having a second width (W2). L is greater than W1, and L is greater than W2. A first stress anchor is formed on the first end sidewall of the first-region channel, and a second stress anchor is formed on the second end sidewall of the first-region channel. The first stress anchor is configured to impart strain through the first end sidewalls to the first-region channel. The second stress anchor is configured to impart strain through the second end sidewalls to the first-region channel.

A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.