There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Aspects of the present disclosure provide a vertical channel 3D semiconductor device sand a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.

Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers. The stack of layers includes a first sub-stack for a first transistor structure. The first sub-stack includes at least three layers of a conductive material separated by one or more layers of a dielectric material. The stack of layers includes a second sub-stack for a second transistor structure. The second sub-stack includes at least three layers of a conductive material separated by one or more layers of a dielectric material. The first and second sub-stacks are separated by dielectric materials. The method includes forming a channel opening in the stack, and providing a first channel structure that includes a semiconductive oxide material aligned with the first transistor structure. The method includes selectively forming a capping layer on the first channel structure, and providing a second channel structure within the channel opening.

A first mask material layer on a Si pillar 7a and a first material layer around a side surface of a top portion of the Si pillar 7a are formed. A second material layer is then formed on an outer periphery of the first material layer. The first mask material layer and the first material layer are then etched by using the second material layer as a mask. A thin SiGe layer, a p.sup.+ layer 23a, and a SiO.sub.2 layer 24a are then formed in a recessed portion formed around the Si pillar 7a. The exposed side surface of the thin SiGe layer is oxidized to form a SiO.sub.2 layer 26a. A TiN layer and a W layer, which are gate conductor layers, are etched by using the SiO.sub.2 layers 24a and 26a as masks to form a TiN layer 29a and a W layer 30a. In plan view, the Si pillar 7a, the p.sup.+ layer 23a with a small diode junction resistance, and the TiN layer 29a and the W layer 30a, which are gate line conductor layers, thus have a self-alignment relationship, and the p.sup.+ layer 23a and the TiN layer 29a are self-aligned with each other with the HfO.sub.2 layer 28 and the SiO.sub.2 layer 26a therebetween in the vertical direction.

According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.