A method of forming an integrated circuit includes placing a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. Placing the first cell layout design includes placing a first active region layout pattern adjacent to a first cell boundary, placing a second active region layout pattern adjacent to a second cell boundary, and placing a first set of active region layout patterns between the first and second active region layout patterns, according to a first set of guidelines. The first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength. In some embodiments, the first, second and first set of active region layout patterns extend in the first direction, and are on a first layout level.

A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.

An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). The P-type FinFETs includes at least one first P-type FinFET and at least one second P-type FinFET. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth that is different from the first depth. A first semiconductor fin of the first P-type FinFET includes a first portion and a second portion that are formed by different materials, and the second portion of the first semiconductor fin has a third depth that is greater than the first depth.

An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). At least one first P-type FinFET includes a silicon germanium (SiGe) channel region. At least one second P-type FinFET includes a Si channel region. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth. The first depth is greater than the second depth.

An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength is disclosed. The ability to vary the exposures of channel structures in 3D transistors from trench isolation allows the drive strengths of the 3D transistors to be varied. Varying the drive strengths of 3D transistors may be advantageous in certain circuit applications to reduce power consumption and/or control drive strength ratios between transistors, as examples. In this regard, in exemplary aspects disclosed herein, during the fabrication of 3D transistors, a trench isolation material is disposed adjacent to channel structures formed from a substrate. The amount of trench isolation material disposed adjacent to each channel structure determines the amount of channel structure surface area exposed to a gate. The amount of channel structure surface area of the 3D transistor exposed to the gate affects the drive strength of the 3D transistor.

An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type and a fourth active region of a fourth set of transistors of a second type. The first, second, third and fourth active regions extend in a first direction, and are in a first level. The first and second active regions are adjacent to a first boundary and have a first width in a second direction. The third active region is adjacent to a second boundary, and has a second width. The fourth active region is between the second active region and the third active region, and has the first width.

An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a silicon germanium channel region. The second P-type FinFET includes a Si channel region. First source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin. A first depth of the first source/drain regions is different from a second depth of the second source/drain regions.