An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a silicon germanium channel region. The second P-type FinFET includes a Si channel region. First source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin. A first depth of the first source/drain regions is different from a second depth of the second source/drain regions.

A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1.sup.st circuit including at least one VFET and provided over at least one gate grid; and a 2.sup.nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1.sup.st circuit, wherein a gate of the VFET of the 1.sup.st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2.sup.nd circuit, and the 1.sup.st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

A semiconductor structure is provided. A logic cell includes a first transistor in a first active region, a second gate electrode and a third gate electrode on opposite sides of the first transistor, a second transistor in a second active region, and a first isolation structure and a second isolation structure on opposite edges of the second active region. The first transistor includes a first gate electrode extending in a first direction. The second and third gate electrodes extend in the first direction, and the first and second isolation structures extend in the first direction. The second transistor and the first transistor share the first gate electrode. The first isolation structure is aligned with the second gate structure in the first direction, and the second isolation structure is aligned with the third gate structure in the first direction.

A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

An integrated circuit device includes a first device and a second device. The first device is disposed within a first circuit region, the first device including a plurality of first semiconductor strips extending longitudinally in a first direction. Adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, which is generally perpendicular to the first direction. The second device is disposed within a second circuit region, the second circuit region being adjacent to the first circuit region in the first direction. The second device includes a second semiconductor strip extending longitudinally in the first direction. A projection of a longitudinal axis of the second semiconductor strip along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips.

The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T.sub.1, a second thickness T.sub.2, and t a third thickness T.sub.3, respectively. The second thickness is greater than the first thickness and the third thickness.

A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.

The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.

In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.