An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region. At least four transistors of a first transistor type and at least four transistors of a second transistor type collectively form part of a logic circuit within the region.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.