A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

The present application discloses a liquid crystal display panel having a plurality of pixels for image display, each of which includes a subpixel region and an inter-subpixel region. The liquid crystal display panel includes an array substrate, a package substrate facing the array substrate, and a liquid crystal layer between the array substrate and the package substrate; a pixel electrode layer and a common electrode layer for applying an electric field for driving the liquid crystal layer, the pixel electrode layer including a plurality of pixel electrodes, the common electrode layer including a plurality of common electrodes; a first electrode signal line layer including a plurality of first electrode signal lines; and a plurality of circuits, each of the plurality of circuits having an output terminal electrically connected to a first electrode signal line of the first electrode signal line layer, an input terminal configured to receive an input voltage, and a control terminal configured to receive a control voltage; at least a portion of the first electrode signal line electrically connected to the output terminal is in the inter-subpixel region of the liquid crystal display panel. The portion of the first electrode signal line in the inter-subpixel region of the liquid crystal display panel is configured to generate an additional electric field with at least one of the common electrode, the pixel electrode, a touch electrode, and another first electrode signal line; the additional electric field is applied to the liquid crystal layer for enhancing light transmittance of the liquid crystal layer.

A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.

An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.

The present application discloses a liquid crystal display panel having a plurality of pixels for image display, each of which includes a subpixel region and an inter-subpixel region. The liquid crystal display panel includes an array substrate, a package substrate facing the array substrate, and a liquid crystal layer between the array substrate and the package substrate; a pixel electrode layer and a common electrode layer for applying an electric field for driving the liquid crystal layer, the pixel electrode layer including a plurality of pixel electrodes, the common electrode layer including a plurality of common electrodes; a first electrode signal line layer including a plurality of first electrode signal lines; and a plurality of circuits, each of the plurality of circuits having an output terminal electrically connected to a first electrode signal line of the first electrode signal line layer, an input terminal configured to receive an input voltage, and a control terminal configured to receive a control voltage; at least a portion of the first electrode signal line electrically connected to the output terminal is in the inter-subpixel region of the liquid crystal display panel. The portion of the first electrode signal line in the inter-subpixel region of the liquid crystal display panel is configured to generate an additional electric field with at least one of the common electrode, the pixel electrode, a touch electrode, and another first electrode signal line; the additional electric field is applied to the liquid crystal layer for enhancing light transmittance of the liquid crystal layer.