Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.

An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

A semiconductor integrated circuit device includes a first power wiring that is formed on a semiconductor substrate and that extends in a first direction, a second power wiring that extends in the first direction such that the second power wiring is separated from the first power wiring, a first diffusion layer that is used for a p-channel type MOSFET and that is formed in a region between the first power wiring and the second power wiring, a second diffusion layer that is used for an n-channel type MOSFET and that is formed on a side of the second power wiring with respect to the first diffusion layer in the region between the first power wiring and the second power wiring, a first gate electrode that extends in a second direction perpendicular to the first direction and that straddles the first diffusion layer, a second gate electrode that extends in the second direction and that straddles the second diffusion layer, and a third diffusion layer for backgates that is formed below at least one of the first power wiring and the second power wiring and that is placed in a dotted manner along the first direction.

A semiconductor device includes a substrate, a first cell and a second cell on the substrate. The first cell includes a first diffusion region in the substrate, a first gate structure over the first diffusion region, and a first contact over the first diffusion region. The first contact is disposed on one side of the first gate structure. The second cell that abuts the first cell includes a second diffusion region in the substrate, a second gate structure over the second diffusion region and a second contact over the second diffusion region. The second contact that is positioned on one side of the second gate structure is adjacent to the first contact of the first cell. The first contact and the second contact are equipotential when the semiconductor device is in operation. The second diffusion region and the first diffusion region form a continuous diffusion region.

To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.