A semiconductor layer includes an opening, and in a joint surface between structures, a portion between a semiconductor layer and an opening in a direction in which the semiconductor layers are stacked together includes a plurality of conductor portions and an insulator portion located between the plurality of conductor portions in a direction orthogonal to the direction.

A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.

A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.

A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.

A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.