In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns.sup.2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

Provided is a solid-state imaging device that suppresses propagation of a crack. There is provided a solid-state imaging device including: a first substrate on which a pixel unit configured to perform photoelectric conversion is formed; and a second substrate on which a logic circuit configured to process a pixel signal outputted from the pixel unit is formed, in which the first and second substrates are laminated by being connected by metal binding between wiring layers that are formed individually, an opening hole is formed on an outer periphery of the pixel unit to penetrate the first and second substrates to reach an upper part of a wire bonding pad formed in the second substrate, the second substrate includes an insulating layer below the wire bonding pad, and the insulating layer includes a first insulating film.

Provided is a solid-state imaging device that suppresses propagation of a crack. There is provided a solid-state imaging device including: a first substrate on which a pixel unit configured to perform photoelectric conversion is formed; and a second substrate on which a logic circuit configured to process a pixel signal outputted from the pixel unit is formed, in which the first and second substrates are laminated by being connected by metal binding between wiring layers that are formed individually, an opening hole is formed on an outer periphery of the pixel unit to penetrate the first and second substrates to reach an upper part of a wire bonding pad formed in the second substrate, the second substrate includes an insulating layer below the wire bonding pad, and the insulating layer includes a first insulating film.

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns.sup.2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

A semiconductor structure includes a supporting layer including a pad area; and a groove formed in the pad area of the supporting layer, wherein a bottom width of the groove is greater than a top width of the groove; and a pad disposed in the pad area on the supporting layer, wherein the pad is partially embedded in the groove. This structure can help to release the bonding pressure during the wire bonding process. When the pad is squeezed out, it can enter the air cavity, which can prevent the protective layer from being lifted up or cracked, and avoid the pad from overflowing. At the same time, the bonding wire squeezed into the air cavity during bonding process increases the contact area between the pad and the supporting layer, thereby enhancing the stability of the overall structure.