A method of forming a semiconductor device according to the present disclosure includes forming a metal-insulator-metal (MIM) structure in a substrate and forming an interconnect structure over the substrate. The MIM structure includes first electrodes of a first polarity and second electrodes of a second polarity. The interconnect structure includes conductive paths electrically connecting to the first and second electrodes. The conductive paths are isolated from each other inside the interconnect structure. The method also includes forming first and second contact pads over the interconnect structure. The first contact pad electrically connects a first portion of the conductive paths corresponding to the first electrodes. The second contact pad electrically connects a second portion of the conductive paths corresponding to the second electrodes.

A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Provided are a resin composition for encapsulation that is superior in high-temperature reverse bias test (HTRB test) reliability; and a semiconductor device. The resin composition for encapsulation is used to encapsulate a power semiconductor element made of Si, SiC, GaN, Ga.sub.2O.sub.3 or diamond, and a cured product of the resin composition for encapsulation has a dielectric tangent of not larger than 0.50 when measured at 150? C. and 0.1 Hz. The semiconductor device is such that a power semiconductor element made of Si, SiC, GaN, Ga.sub.2O.sub.3 or diamond is encapsulated by the cured product of the resin composition for encapsulation.

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

a p-type amorphous oxide semiconductor including gallium, a method of manufacturing the same, a solar cell including the same and a method of manufacturing the solar cell are disclosed. The p-type oxide semiconductor where gallium (Ga) is further combined with combination of one or more components selected from a group of CuS, SnO, ITO, IZTO, IGZO and IZO is provided.