Patent classifications
H01L2224/05111
Semiconductor contact structure having stress buffer layer formed between under bump metal layer and copper pillar
Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.
Semiconductor device and semiconductor package
A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.
Semiconductor device and semiconductor package
A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.
Semiconductor device including through substrate vias and method of manufacturing the semiconductor device
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.
Semiconductor device including through substrate vias and method of manufacturing the semiconductor device
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.
Pillar-last methods for forming semiconductor devices
Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.
Pillar-last methods for forming semiconductor devices
Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.
DISPLAY DEVICE
A display device includes: a circuit substrate including a plurality of pixel circuit units and a plurality of pads on a first surface thereof, the plurality of pads being electrically connected to the pixel circuit units; a display substrate on the circuit substrate and including a plurality of light emitting elements electrically connected to the pixel circuit units; a circuit board on the circuit substrate and including a plurality of circuit board pads electrically connected to the pads; a heat dissipation substrate on a second surface of the circuit substrate, the second surface being opposite to the first surface; and a cover substrate on the heat dissipation substrate and partially overlapping the circuit substrate and the circuit board. Each of the plurality of pads is in direct contact with at least one of the plurality of circuit board pads.
LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE HAVING THE SAME
A light emitting device including a substrate having a protruding pattern on an upper surface thereof, a first sub-unit disposed on the substrate, a second sub-unit disposed between the substrate and the first sub-unit, a third sub-unit disposed between the substrate and the second sub-unit, a first insulation layer at least partially in contact with side surfaces of the first, second, and third sub-units, and a second insulation layer at least partially overlapping with the first insulation layer, in which at least one of the first insulation layer and the second insulation layer includes a distributed Bragg reflector.
DISPLAY DEVICE
A display device comprises a substrate, a plurality of pixel electrodes on the substrate, and a plurality of light emitting elements on the plurality of pixel electrodes, wherein the plurality of light emitting elements include a first light emitting element and a second light emitting element, and each of the first light emitting element and the second light emitting element comprises a first stack configured to emit a first light, a second stack below the first stack and configured to emit a second light or a third light, and tunnel functional layers between the first stack and the second stack.