Semiconductor devices, such as vertical-cavity surface-emitting lasers, and methods for manufacturing the same, are disclosed. The semiconductor devices include contact extensions and electrically conductive adhesive material, such as fusible metal alloys or electrically conductive composites. In some instances, the semiconductor devices further include structured contacts. These components enable the production of semiconductor devices having minimal distortion. For example, arrays of vertical-cavity surface-emitting lasers can be produced exhibiting little to no bowing. Semiconductor devices having minimal distortion exhibit enhanced performance in some instances.

A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.

A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

There is disclosed a method for manufacturing a semiconductor device comprising a semiconductor chip having a connection portion and a wiring circuit board having a connection portion, the respective connection portions being electrically connected to each other, or a semiconductor device comprising a plurality of semiconductor chips having connection portions, the respective connection portions being electrically connected to each other. The connection portions consist of metal. The above described method comprises: (a) a first step of press-bonding the semiconductor chip and the wiring circuit board or the semiconductor chips to each other so that the respective connection portions are in contact with each other with a semiconductor adhesive interposed therebetween, at a temperature lower than a melting point of the metal of the connection portion, to obtain a temporarily connected body; (b) a second step of sealing at least a part of the temporarily connected body with a sealing resin to obtain a sealed temporarily connected body; and (c) a third step of heating the sealed temporarily connected body at a temperature equal to or higher than the melting point of the metal of the connection portion, to obtain a sealed connected body.