In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure including a second bonding oxide layer having second metallic structure embedded therein are provided. A high-k dielectric material is formed on a surface of the first metallic structure. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. The nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layers and either a nitridized high-k dielectric material located in at least an upper portion of the high k dielectric material or a nitridized metallic region located in an upper portion of the second metallic structure. The nitrogen within the nitridized metallic region is then selectively removed to restore the upper portion of the second metallic structure to its original composition. Bonding is then performed.