A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.

In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.

A structure including a solder layer has a substrate, a solder layer formed on the substrate, and an under barrier metal formed as an alloy layer containing Fe and Co between the substrate and the solder layer. An internal stress of the under barrier metal is 260 Mpa or less. The structure having an under barrier metal and a solder layer is produced by successively forming on the substrate, the under barrier metal and the solder layer by a plating method.

In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.