A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.