A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

A problem addressed by an embodiment of the present invention lies in providing a UBM structure which includes thin layers and can prevent diffusion of solder into an electrode. The UBM structure according to an embodiment of the present invention includes: a first UBM layer on an electrode, a second UBM layer on the first UBM layer, and a passivated metal layer between the first UBM layer and the second UBM layer. The passivated metal layer functions as a barrier layer with respect to solder diffusion.

A problem addressed by an embodiment of the present invention lies in providing a UBM structure which includes thin layers and can prevent diffusion of solder into an electrode. The UBM structure according to an embodiment of the present invention includes: a first UBM layer on an electrode, a second UBM layer on the first UBM layer, and a passivated metal layer between the first UBM layer and the second UBM layer. The passivated metal layer functions as a barrier layer with respect to solder diffusion.

A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.