A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

A semiconductor device includes: a semiconductor layer formed on a substrate; a first resin layer formed on the semiconductor layer; a second resin layer formed on the first resin layer; a first wiring layer that is formed on the semiconductor layer and is buried in the second resin layer; a second wiring layer that is formed on the second resin layer and the first wiring layer, and is electrically connected to the first wiring layer; and a first inorganic insulating film covering the second resin layer and the second wiring layer, wherein an area of the first wiring layer is larger than an area of the second wiring layer.

A semiconductor device includes: a semiconductor layer formed on a substrate; a first resin layer formed on the semiconductor layer; a second resin layer formed on the first resin layer; a first wiring layer that is formed on the semiconductor layer and is buried in the second resin layer; a second wiring layer that is formed on the second resin layer and the first wiring layer, and is electrically connected to the first wiring layer; and a first inorganic insulating film covering the second resin layer and the second wiring layer, wherein an area of the first wiring layer is larger than an area of the second wiring layer.

A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

A bond pad structure includes a first oxide layer that overlies a substrate. A plurality of adhesion structures are formed over the first oxide layer. A second oxide layer is formed over the plurality of adhesion structures and the first oxide layer. Each one of a plurality of contact openings formed within a surface region of the second oxide layer includes one or more sides and is aligned over at least a portion of a top surface of a corresponding one of the plurality of adhesion structures. A barrier layer is formed within the surface region that is over the second oxide layer and within the plurality of contact openings and over the at least a portion of the top surface of the corresponding ones of the plurality of adhesion structures. A metal layer is formed over the barrier layer.

A bond pad structure includes a first oxide layer that overlies a substrate. A plurality of adhesion structures are formed over the first oxide layer. A second oxide layer is formed over the plurality of adhesion structures and the first oxide layer. Each one of a plurality of contact openings formed within a surface region of the second oxide layer includes one or more sides and is aligned over at least a portion of a top surface of a corresponding one of the plurality of adhesion structures. A barrier layer is formed within the surface region that is over the second oxide layer and within the plurality of contact openings and over the at least a portion of the top surface of the corresponding ones of the plurality of adhesion structures. A metal layer is formed over the barrier layer.

An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.