H01L2224/05178

Low-temperature bonding with spaced nanorods and eutectic alloys

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

Semiconductor chip, electronic device including the same, and method of connecting the semiconductor chip to the electronic device

A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

Semiconductor chip, electronic device including the same, and method of connecting the semiconductor chip to the electronic device

A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

Two-component bump metallization

A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure.

Two-component bump metallization

A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate.

Microstructure modulation for metal wafer-wafer bonding

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

Microstructure modulation for metal wafer-wafer bonding

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

Substrate, electronic device and display device having the same

A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base substrate, an insulating layer including a plurality of contact holes exposing a portion of the first conductive pattern, and second conductive patterns separately on the insulating layer and connected to the first conductive pattern through the plurality of contact holes, wherein side surfaces of the second conductive patterns are exposed.

Substrate, electronic device and display device having the same

A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base substrate, an insulating layer including a plurality of contact holes exposing a portion of the first conductive pattern, and second conductive patterns separately on the insulating layer and connected to the first conductive pattern through the plurality of contact holes, wherein side surfaces of the second conductive patterns are exposed.

SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION
20240071973 · 2024-02-29 ·

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.