Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

A semiconductor package includes: a substrate including an insulating layer, a plurality of pads on the insulating layer, a surface protective layer covering the insulating layer and having first through-holes exposing at least a portion of the insulating layer and second through-holes exposing at least a portion of each of the plurality of pads, a plurality of first dummy patterns extending from the plurality of pads to the first through-holes, and a plurality of second dummy patterns extending from the first through-holes to an edge of the insulating layer; a semiconductor chip on the substrate and including connection terminals electrically connected to the plurality of pads exposed through the second through-holes; and an encapsulant encapsulating at least a portion of the semiconductor chip and filling the first through-holes, wherein a separation distance between the first through-holes is greater than a separation distance between the second through-holes.

A light emitting diode (LED) includes a n-doped semiconductor material layer, a p-doped semiconductor material layer, an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer, and a photonic crystal grating configured to increase the light extraction efficiency of the LED.

A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor group and a second conductor group, and the second conductive contact pad includes a third conductor group and a fourth conductor group.

A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.

A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.