Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/04
Structure, shape, material or disposition of the bonding areas prior to the connecting process
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H01L2224/05
of an individual bonding area
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H01L2224/056
with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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H01L2224/05617
the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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H01L2224/0562
Antimony [Sb] as principal constituent
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H01L2224/0562

Phase change interconnects and methods for forming the same
12500191 · 2025-12-16 · ·

A structure of a semiconductor package is disclosed. The structure includes a first substrate including a first interconnect structure. The structure includes a second substrate including a second interconnect structure, the second substrate bonded to the first substrate. The structure includes a connection pad interposed between the first interconnect structure and the second interconnect structure. The connection pad includes a material configured to switch between a high resistance state and a low resistance state. The material of the connection pad includes a phase change material.