A method of forming a sandwich passivation layer (405) on a semiconductor device (400) comprising a bond pad (404) is provided. The method comprises forming a first layer (406) over a surface of the semiconductor device (400), removing a part of the first layer (406) to expose a surface of the bond pad (404), forming a second layer (407) over the first layer (406) and the surface of the bond pad (404), and forming a third layer (408) over the second layer (407), wherein the surface of the bond pad (404) is not in contact with the first layer (406) or third layer (408).

A semiconductor module includes a first power semiconductor device, a conductive wire, and a resin film. The conductive wire is joined to a surface of a first front electrode of the first power semiconductor device. The resin film is formed to be continuous on at least one of an end portion or an end portion of a first joint between the first front electrode and the conductive wire in a longitudinal direction of the conductive wire, a surface of the first front electrode, and a surface of the conductive wire. The resin film has an elastic elongation rate of 4.5% to 10.0%.

A semiconductor module includes a first power semiconductor device, a conductive wire, and a resin film. The conductive wire is joined to a surface of a first front electrode of the first power semiconductor device. The resin film is formed to be continuous on at least one of an end portion or an end portion of a first joint between the first front electrode and the conductive wire in a longitudinal direction of the conductive wire, a surface of the first front electrode, and a surface of the conductive wire. The resin film has an elastic elongation rate of 4.5% to 10.0%.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

A display device is provided. The display device comprising: a substrate including a display area and a pad area, a first conductive layer disposed on the substrate and including a first signal line disposed in the display area, a buffer layer disposed on the first conductive layer, a semiconductor layer disposed on the buffer layer in the display area, a gate insulating film disposed on the semiconductor layer, a second conductive layer disposed on the gate insulating film and including a gate electrode overlapping the semiconductor layer in the display area, a first electrode of a transistor disposed to overlap one side of the semiconductor layer in the display area and connected to the first signal line through a contact hole penetrating through the buffer layer and the gate insulating film, and a second electrode of the transistor disposed to overlap the other side of the semiconductor layer in the display area, a first pad disposed on the buffer layer in the pad area and exposed by a pad opening, a first insulating layer disposed on the second conductive layer and the first pad, and a light emitting element disposed on the first insulating layer in the display area, wherein the first pad is formed of the first conductive layer or the second conductive layer.

A display device includes a first planarization film including an opening, a reflective film provided on an inclined surface inside the opening in the first planarization film, an LED chip surrounded by the reflective film and provided inside the opening, and a second planarization film provided on the first planarization film, surrounding the LED chip, and filling the opening, wherein a height from an upper end of the inclined surface of the first planarization film to an interface with air in the second planarization film is 20 μm or less.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.