According to an embodiment, a temperature of an inside of a furnace is set to fall within a range of a reduction temperature or more of a carboxylic acid and less than a melting temperature of a solder bump, and the inside is concurrently set to have a first carboxylic acid gas concentration. Thereafter, the temperature of the inside is raised up to the melting temperature, and the inside is concurrently set to have a second carboxylic acid gas concentration. The second carboxylic acid gas concentration is lower than the first carboxylic acid gas concentration, and is a concentration containing a minimum amount of carboxylic acid gas defined to achieve reduction on an oxide film of the solder bump. The inside has the second carboxylic acid gas concentration at least at a time when the temperature of the inside reaches the melting temperature.

According to an embodiment, a temperature of an inside of a furnace is set to fall within a range of a reduction temperature or more of a carboxylic acid and less than a melting temperature of a solder bump, and the inside is concurrently set to have a first carboxylic acid gas concentration. Thereafter, the temperature of the inside is raised up to the melting temperature, and the inside is concurrently set to have a second carboxylic acid gas concentration. The second carboxylic acid gas concentration is lower than the first carboxylic acid gas concentration, and is a concentration containing a minimum amount of carboxylic acid gas defined to achieve reduction on an oxide film of the solder bump. The inside has the second carboxylic acid gas concentration at least at a time when the temperature of the inside reaches the melting temperature.

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

The present application discloses a method for fabricating a semiconductor device with a connection structure. The method includes providing a first semiconductor structure comprising a plurality of first conductive features adjacent to a top surface of the first semiconductor structure; forming a connection structure comprising a connection insulating layer on the top surface of the first semiconductor structure, a connection layer in the connection insulating layer, and a plurality of first porous interlayers on the plurality of first conductive features and in the connection insulating layer; and forming a second semiconductor structure comprising a plurality of second conductive features on the plurality of first porous interlayers.