A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.

A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.

A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir.

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads, the semiconductor chip includes a passivation layer having openings exposing at least portions of the connection pads, the redistribution layer of the second interconnection member is connected to the connection pad through a via, a metal layer is disposed between the connection pad and the via, and the metal layer covers at least a portion of the connection pad.

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.

A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.