A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

An electronic circuit including a surface intended to be attached to another electronic circuit by hybrid molecular bonding. The electronic circuit includes an electrically-insulating layer exposed on the surface, and, distributed in the electrically-insulating layer, first electrically-conductive bonding pads exposed on a first portion of the surface, the density of the first bonding pads on the first portion of the surface being smaller than 30%, and at least one electrically-conductive test pad, exposed on a second portion of the surface containing a square having a side length greater than 30 ?m. The density of electrically-conductive material of the test pad exposed on the second portion of the surface is in the range from 40% to 80%.

An electronic circuit including a surface intended to be attached to another electronic circuit by hybrid molecular bonding. The electronic circuit includes an electrically-insulating layer exposed on the surface, and, distributed in the electrically-insulating layer, first electrically-conductive bonding pads exposed on a first portion of the surface, the density of the first bonding pads on the first portion of the surface being smaller than 30%, and at least one electrically-conductive test pad, exposed on a second portion of the surface containing a square having a side length greater than 30 ?m. The density of electrically-conductive material of the test pad exposed on the second portion of the surface is in the range from 40% to 80%.

A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, a TFT structure, a bonding line, a bonding pad, and a luminescent functional layer. The substrate includes a display area and a pad area. The TFT structure is disposed on the substrate in the display area. The bonding line is disposed on the substrate in the pad area. The bonding pad is disposed on a side of the bonding line away from the substrate. The bonding pad includes a thin film for blocking moisture and oxygen. The luminescent functional layer is disposed on a side of the TFT structure away from the substrate. The thin film for blocking moisture and oxygen is disposed on the bonding line, thereby blocking moisture and oxygen from corroding the bonding line.

A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

The proposed device includes a first chip (102) comprising a superconducting quantum bit and a second chip (104) bonded to the first chip, the second chip including a substrate (108) having first and second opposing surfaces. The first surface (101) facing the first chip includes a layer (105) of superconductor material which includes a first circuit element. The second chip further includes a second layer (107) on the second surface (103) which includes a second circuit element, and a through connector (109) that extends from the first surface to the second surface and electrically connects a portion of the superconductor material layer to the second circuit element.