A cryogenic electronic package includes a circuitized substrate, an interposer, a superconducting multichip module (SMCM) and at least one superconducting semiconductor structure. The at least one superconducting semiconductor structure is disposed over and coupled to the SMCM, and the interposer is disposed between the SMCM and the substrate. The SMCM and the at least one superconducting semiconductor structure are electrically coupled to the substrate through the interposer. A cryogenic electronic assembly including a plurality of cryogenic electronic packages is also provided.

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

Provided is a display substrate, which includes a base substrate, a circuit structure layer disposed on the base substrate, multiple ultrasonic sensing elements and multiple micro light-emitting elements. The multiple ultrasonic sensing elements are disposed on a side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer, and the multiple light-emitting elements are disposed on the side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer. An orthographic projection of the multiple ultrasonic sensing elements on the base substrate does not overlap with an orthographic projection of the multiple micro light-emitting elements on the base substrate.