Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.